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?2012 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.5 features ? high current drive capability (200ma) ? adjustable duty cycle ? temperature stability of 0.005%/ ? c ? timing from ? sec to hours ? turn off time less than 2 ? sec applications ? precision timing ? pulse generation ? time delay generation ? sequential timing description the lm555 is a highly stable controller capable of produc- ing accurate timing pulses. with a monostable operation, the time delay is controlled by one external resistor and one capacitor. with an astable oper ation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor. 8-dip 8-soic 1 1 internal block diagram f/f output stage 1 7 5 2 3 4 6 8 rrr comp. comp. discharging tr. vref vcc discharge threshold control voltage gnd trigger output reset lm555 single timer
lm555 2 absolute maximum ratings (t a = 25 ? c) parameter symbol value unit supply voltage v cc 16 v lead temperature (soldering 10sec) t lead 300 ? c power dissipation p d 600 mw operating temperature range (lm555) t opr 0 ~ +70 ? c storage temperature range t stg -65 ~ +150 ? c
lm555 3 electrical characteristics (t a = 25 ? c, v cc = 5 ~ 15v, unless otherwise specified) notes: 1. when the output is high, the supply current is typically 1ma less than at v cc = 5v. 2. tested at v cc = 5.0v and v cc = 15v. 3. this will determine the maximum value of r a + r b for 15v operation, the max. total r = 20m ? , and for 5v operation, the max. total r = 6.7m ?? 4. these parameters, although guarante ed, are not 100% tested in production. parameter symbol conditions min. typ. max. unit supply voltage v cc -4.5-16v supply current (low stable) (note1) i cc v cc = 5v, r l = ? -36ma v cc = 15v, r l = ? -7.515 ma timing error (monostable) initial accuracy (note2) drift with temperature (note4) drift with supply voltage (note4) accur ? t/ ? t ? t/ ? v cc r a = 1k ? to100k ? c = 0.1 ? f -1.0 50 0.1 3.0 0.5 % ppm/ ? c %/v timing error (astable) intial accuracy (note2) drift with temperature (note4) drift with supply voltage (note4) accur ? t/ ? t ? t/ ? v cc r a = 1k ? to 100k ? c = 0.1 ? f - 2.25 150 0.3 -% ppm/ ? c %/v control voltage v c v cc = 15v 9.0 10.0 11.0 v v cc = 5v 2.63.334.0 v threshold voltage v th v cc = 15v - 10.0 - v v cc = 5v - 3.33 - v threshold current (note3) i th - - 0.1 0.25 ? a trigger voltage v tr v cc = 5v 1.1 1.67 2.2 v v cc = 15v 4.5 5 5.6 v trigger current i tr v tr = 0v 0.01 2.0 ? a reset voltage v rst - 0.4 0.7 1.0 v reset current i rst - 0.1 0.4 ma low output voltage v ol v cc = 15v i sink = 10ma i sink = 50ma -0.06 0.3 0.25 0.75 v v v cc = 5v i sink = 5ma -0.050.35 v high output voltage v oh v cc = 15v i source = 200ma i source = 100ma 12.75 12.5 13.3 -v v v cc = 5v i source = 100ma 2.75 3.3 - v rise time of output (note4) t r - -100- ns fall time of output (note4) t f - -100- ns discharge leakage current i lkg - -20100na
lm555 4 application information table 1 below is the basic operating table of 555 timer: when the low signal input is ap plied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. only when the high signal is applied to the reset terminal , the timer's output changes according to threshold voltage and trigger voltage. when the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. during this time, the timer output is maintained low. later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's inter nal discharge tr. turns off, increasing the threshold voltage and driving the timer output again at high. 1. monostable operation table 1. basic operating table threshold voltage (v th )(pin 6) trigger voltage (v tr )(pin 2) reset(pin 4) output(pin 3) discharging tr. (pin 7) don't care don't care low low on v th > 2vcc / 3 v th > 2vcc / 3 high low on vcc / 3 < v th < 2 vcc / 3 vcc / 3 < v th < 2 vcc / 3 high - - v th < vcc / 3 v th < vcc / 3 high high off 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 -3 10 -2 10 -1 10 0 10 1 10 2 10m ? 1m ? 10k ? 1 00 k ? r a =1k ? capacitance(uf) time delay(s) figure 1. monostable circuit figure 2. resistance and capacitance vs. time delay(t d ) figure 3. waveforms of monostable operation 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r a c1 c2 r l trigger
lm555 5 figure 1 illustrates a monostable circuit. in this mode, the timer generates a fixed pulse whenever the trigger voltage falls below vcc/3. when the trigger pu lse voltage applied to the #2 pin falls below v cc/3 while the timer output is low, the timer's internal flip-flop turns the discharging tr. off and causes the timer output to become high by charging the external capacitor c1 and setting the flip-flop output at the same time. the voltage across the external capacitor c1, v c1 increases exponentially with the time constant t=r a *c and reaches 2vcc/3 at td=1.1r a *c. hence, capacitor c1 is charged through resistor r a . the greater the time constant r a c, the longer it takes for the v c1 to reach 2vcc/3. in other words, the time constant r a c controls the output pulse width. when the applied voltage to the capacitor c1 reaches 2vcc/3, the comparator on the trigger terminal rese ts the flip-flop, turning the discharging tr. on. at this time, c1 begins to discharge and the timer output converts to low. in this way, the timer operating in the monostable repeats the above process. figure 2 shows the time constant relationship based on r a and c. figure 3 shows the general waveforms during the monostable operation. it must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of vcc/3 before the timer output turns low. that is, although the output remains unaffected even if a different trigger pulse is applied while the outpu t is high, it may be affected and the waveform does not operate prope rly if the trigger pulse voltage at the end of the output pulse remains at below vcc/3. figure 4 shows such a timer output abnormality. 2. astable operation figure 4. waveforms of mono stable operation (abnormal) 100m 1 10 100 1k 10k 100k 1e-3 0.01 0.1 1 10 100 1 0 m ? 1 m ? 1 00 k ? 1 0 k ? 1 k ? (r a +2r b ) capacitance(uf) frequency(hz) figure 5. astable circuit figure 6. capacitance and resistance vs. frequency 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r a c1 c2 r l r b
lm555 6 an astable timer operation is achieved by adding resistor r b to figure 1 and configuring as shown on figure 5. in the astable operation, the trigger terminal and the thre shold terminal are connected so that a se lf-trigger is formed, operating as a multi vibrator. when the timer output is high, its internal discharging tr. turns off and the v c1 increases by exponential function with the time constant (r a +r b )*c. when the v c1 , or the threshold voltage, reaches 2vcc/3, the comparator output on the trigger te rminal becomes high, resetting the f/f and causing the timer output to become low. this in turn turns on the discharging tr. and the c1 discharges through the discharging channel formed by r b and the discharging tr. when the v c1 falls below vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. the discharging tr. turns off and the v c1 rises again. in the above process, the section where the time r output is high is the time it takes for the v c1 to rise from vcc/3 to 2vcc/3, and the section where the timer output is low is the time it takes for the v c1 to drop from 2vcc/3 to vcc/3. when timer output is high, the equivalent circuit for charging capacitor c1 is as follows: since the duration of the timer output high state(t h ) is the amount of time it takes for the v c1 (t) to reach 2vcc/3, figure 7. waveforms of astable operation vcc r a r b c1 vc1 (0-)=vcc/ 3 c 1 dv c1 dt ------------- v cc v0- ?? ? r a r b + ------------------------------- = 1 ?? v c1 0+ ?? v cc 3 ? = 2 ?? v c1 t ?? v cc 1 2 3 -- - e - t r a r b + ?? c1 ------------------------------------ ? ?? ?? ? ?? ?? ?? ?? = 3 ??
lm555 7 the equivalent circuit for disc harging capacitor c1, when timer output is low is, as follows: since the duration of the timer output low state( t l ) is the amount of time it takes for the v c1 (t) to reach vcc/3, since r d is normally r b >>r d although related to the size of discharging tr., t l =0.693r b c 1 (10) consequently, if the timer operates in astable, the period is the same with 't=t h +t l =0.693(ra+r b )c 1 +0.693r b c 1 =0.693(r a +2r b )c 1 ' because the period is the sum of the charge time and discharge time. and since frequency is the recipro cal of the period, the following applies. 3. frequency divider by adjusting the length of the timing cycle, the basic circuit of figure 1 can be made to operate as a frequency divider. figur e 8. illustrates a divide-by-three circuit that makes use of th e fact that retriggering cannot occur during the timing cycle. v c1 t ?? 2 3 -- - v cc v = cc 1 2 3 -- - e - t h r a r b + ?? c1 ------------------------------------ ? ?? ?? ?? ? ?? ?? ?? ?? ?? = 4 ?? t h c 1 r a r b + ?? in2 0.693 r a r b + ?? c 1 = = 5 ?? c 1 dv c1 dt -------------- 1 r a r b + ----------------------- v c1 0 = + 6 ?? v c1 t ?? 2 3 -- - v cc e - t r a r d + ?? c1 ------------------------------------ - = 7 ?? 1 3 -- - v cc 2 3 -- - v cc e - t l r a r d + ?? c1 ------------------------------------ - = 8 ?? t l c 1 r b r d + ?? in2 0.693 r b r d + ?? c 1 = = 9 ?? frequency, f 1 t --- 1.44 r a 2r b + ?? c 1 --------------------------------------- - == 11 ??
lm555 8 4. pulse width modulation the timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. figure 9 illustrates the pulse width modulation circuit. when the continuous trigger pulse train is applied in the mono stable mode, the timer output width is modulated according to the signal applied to the control terminal. sine wave as well as other waveforms may be applied as a signal to the control terminal. figure 10 shows the example of pulse width modulation waveform. 5. pulse position modulation if the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in figure 11, the timer becomes a pulse position modulator. in the pulse position modulator, the reference of the timer's in ternal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used. figure 8. waveforms of frequency divider operation figure 9. circuit for pulse width modulation figure 10. waveforms of pulse width modulation 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc trigger r a c output input
lm555 9 6. linear ramp when the pull-up resistor ra in the monos table circuit shown in figure 1 is repl aced with constant cu rrent source, the v c1 increases linearly, generating a linear ramp. figure 13 shows the linear ramp generating circuit and figure 14 illustrates the generated linear ramp waveforms. in figure 13, current source is created by pnp transistor q1 and resistor r1, r2, and r e . for example, if vcc=15v, r e =20k ? , r1=5kw, r2=10k ? , and v be =0.7v, v e =0.7v+10v=10.7v ic=(15-10.7)/20k=0.215ma 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc r a c r b modulation output figure 11. circuit for pu lse position modulation figure 12. waveforms of pulse position modulation figure 13. circuit for linear ramp figure 14. waveforms of linear ramp 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc c2 r1 r2 c1 q1 output r e i c v cc v e ? r e --------------------------- = 12 ?? here, v e is v e v be r 2 r 1 r 2 + --------------------- - v cc + = 13 ??
lm555 10 when the trigger starts in a timer conf igured as shown in figure 13, the curr ent flowing through cap acitor c1 becomes a constant current generated by pnp transistor and resistors. hence, the v c is a linear ramp function as shown in figure 14. the gradient s of the linear ramp function is defined as follows: here the vp-p is the peak-to-peak voltage. if the electric charge amount accu mulated in the capac itor is divided by th e capacitance, the v c comes out as follows: v=q/c (15) the above equation divided on both sides by t gives us and may be simplified into the following equation. s=i/c (17) in other words, the gradient of the linear ramp function app earing across the capacitor can be obtained by using the constant current flowing thro ugh the capacitor. if the constant current flow through the capacitor is 0.215 ma and the capacitance is 0.02 ? f, the gradient of the ramp function at both ends of the capacitor is s = 0.215m/0.022 ? = 9.77v/ms. s v pp ? t ---------------- = 14 ?? v t --- - qt ? c ----------- - = 16 ??
lm555 11 mechanical dimensions package dimensions in millimeters c 7 typ 7 typ .430 max [10.92] b a .400 .373 [ 10.15 9.46 ] .250.005 [6.350.13] .036 [0.9 typ] .070 .045 [ 1.78 1.14 ] .100 [2.54] .300 [7.62] .060 max [1.52] .310.010 [7.870.25] .130.005 [3.30.13] .210 max [5.33] .140 .125 [ 3.55 3.17 ] .015 min [0.38] .021 .015 [ 0.53 0.37 ] .010 +.005 -.000 [ 0.254 +0.127 -0.000 ] pin #1 pin #1 (.032) [r0.813] (.092) [?2.337] top view option 1 top view option 2 .001[.025] c n08erevg c. does not include mold flash or protrusions. dambar protrusions shall not exceed d. does not include dambar protrusions. b. controling dimensions are in inches a. conforms to jedec registration ms-001, mold flash or protrusions shall not exceed variations ba e. dimensioning and tolerancing notes: reference dimensions are in millimeters .010 inches or 0.25mm. .010 inches or 0.25mm. per asme y14.5m-1994. 8-dip
lm555 12 mechanical dimensions (continued) package dimensions in millimeters 8-soic
lm555 9/25/12 0.0m 001 stock#dsxxxxxxxx ? 2012 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain lif e, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in an y component of a life support device or system whose fa ilure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve re liability, function or design. fairchild does not assume any liability arising out of the applic ation or use of any product or circuit described herein; neither does it convey any license under its pat ent rights, nor the rights of others. ordering information product number operating temperature range package packing method lm555cn 0 ~ +70 ? c dip 8l rail lm555cm soic 8l rail lm555cmx soic 8l tape & reel

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